The present invention relates to a semiconductor memory device which supplies, by means of a voltage bootstrap, a signal voltage higher than a power source voltage, to a selection line (a word or bit line) of a memory cell, when the memory cell is selected.
In a semiconductor memory device, particularly a dynamic RAM (Random Access Memory), a WRITE voltage for a memory cell must be sufficiently close to a power source voltage, in order to increase the operation speed and the time margin for reading data. For this purpose, in some semiconductor memory devices, a voltage bootstrap circuit is provided to output a signal voltage, higher than a power source voltage, to a selected word or bit line.
FIG. 1 is a block diagram showing a configuration of a conventional semiconductor memory device with such a voltage bootstrap circuit. The configuration of FIG. 1 is also shown in T. Nakano et al, "A Sub-100 ns 256K DRAM with Open Bit Line Scheme", IEEE Journal of Solid-State Circuits, Vol. SC-18, No. 5 (October, 1983), p. 453, FIG. 3. Pages 452 to 456 of this literature are incorporated in the present application.
Referring to FIG. 1, reference numeral 10 denotes a dynamic memory cell array having a plurality of memory cells each consisting of a selection MOS transistor and a capacitor for storing data. The memory cells in memory cell array 10 are connected to a plurality of word lines 11R, respectively. When lines 11R are driven, all the memory cells connected thereto are selected simultaneously. Reference numeral 12R denotes a row decoder for selecting word lines 11R in accordance with address signals. Row decoder 12R receives output signal OUT whose magnitude is increased, by voltage bootstrap circuit 13, to be higher than the power source voltage. Decoder 12R drives word line 11R, selected in accordance with an address signal, by signal OUT.
Voltage bootstrap circuit 13 receives a RAS (row address strobe) signal or a control signal for an auto-refresh operation, as input signal IN, and outputs signal OUT which is increased to be higher than the power source voltage when the level of input signal IN is changed.
Each of the memory cells in memory cell array 10 is connected, in a unit of a word line, to a corresponding one of a plurality of sense amplifiers (not shown), via a pair of bit lines. The sense amplifiers are connected to column decoders (not shown). The data stored in the memory cells, which are each connected to a specific word line 11R selected by row decoder 12R, are sensed by the corresponding sense amplifiers. Some of the sensed data are selected by a column decoder. When data is read out, data selected by the column decoder is externally output. When data is written in, new WRITE data is supplied to the column decoder.
When a highly increased voltage is supplied to selected word line 11R, the speed for reading data from a selected memory cell can be increased. Alternatively, the impedance of a transistor for selecting a memory cell may be decreased, thereby charging a capacitor, for data storage, with a voltage sufficiently close to the power source voltage.
FIG. 2 is a circuit diagram showing an example of voltage bootstrap circuit 13 shown in FIG. 1; and FIGS. 3A to 3D are timing charts explaining the operations of voltage bootstrap circuit 13. In the arrangement of FIG. 2, capacitor 21 is precharged, via n-channel MOS transistor 20 serving as a load, to a potential lower than positive power source voltage VDD, by gate threshold voltage VTH of MOS transistor 20. In this precharged state, when input signal IN (FIG. 3A) is set at a low potential (VSS) and the output of inverter 26 is set at a high potential, the potential of node N1 is increased by precharged capacitor 21, and is set at VDD+.DELTA.V2 (where .DELTA.V2 is a voltage sufficiently higher than gate threshold voltage VTH of MOS transistor 20) (FIG. 3C). N-channel MOS transistor 22 is turned on by the increased potential of node N1, and capacitor 23 is charged via MOS transistor 22 until node N2 is set at power source potential VDD (FIG. 3B). In this case, if output control signals CONT1 and CONT2 are at low and high potentials VSS and VDD, respectively, and n-channel MOS transistors 24 and 25 are turned off and on by signals CONT1 and CONT2, respectively, the potential of signal OUT at output node N3 becomes VSS (FIG. 3D).
When the potential of input signal IN is increased from VSS to VDD, the output potential of inverter 26 drops inversely from VDD to VSS. Then, the potential of node N1 is decreased from VDD+.DELTA.V2 to VDD-VTH by the coupling of capacitor 21, thereby turning off MOS transistor 22.
In accordance with the output potential drop of inverter 26, the output potential of inverter 27 increases from VSS to VDD, and the potential of node N2 is increased from VDD to VDD+.DELTA.V1 by the coupling of precharged capacitor 23. Meanwhile, in synchronism with the leading edge of input signal IN, the potential of output control signal CONT1 is increased from VSS to VDD, and then the signal line of signal CONT1 is set in a high impedance state. The potential of output control signal CONT2 drops from VDD to VSS in synchronism with the leading edge of input signal IN, thereby turning off MOS transistor 25. As a result, MOS transistor 24 is turned on, and the potential of node N2 is obtained, from output node N3, as output signal OUT. More specifically, when the line impedance of signal CONT1 is set at high level, the gate potential of MOS transistor 24 is increased by the coupling of capacitor 28, inserted between the gate of MOS transistor 24 and output node N3. This increased gate potential turns on MOS transistor 24, and the increased potential VDD+.DELTA.V1 of node N2 is sent to output node N3, without modification of the potential.
Subsequently, when the potential of signal IN drops from VDD to VSS, the potentials of signals CONT1 and CONT2 are set at VSS and VDD, respectively, so that MOS transistors 24 and 25 are turned off and on, respectively. Then, the potential of node N3 drops to VSS, via MOS transistor 25. On the other hand, the output potentials of inverters 26 and 27 are set at VDD and VSS, respectively, and the potential of node N1 is increased again to VDD+.DELTA.V2. As a result, MOS transistor 22 is turned on, so as to charge capacitor 23 to almost VDD.
After capacitor 23 is discharged, the potential of node N2 is decreased to about (1/2) to (2/3) VDD. The time period (tl of FIG. 3B) required for increasing the potential of node N2 to about VDD is normally about 20 to 30 nsec at shortest, and depends on the element dimensions of MOS transistor 22.
In the conventional memory device shown in FIG. 1, when continuous data readout or data write-in is to be performed, a time interval of at least 20 to 30 nsec is required between two sequential operations which are adjacent in time, in order to fully charge capacitor 23. If such a time interval is not provided and the next operation is started without sufficiently charging the capacitor (23), the potential of word lines goes lower than a prescribed value, and the conductance of a MOS transistor for memory cell selection becomes small. Then, a sense amplifier is operated before a sufficient potential difference occurs in the bit lines, thereby causing an erroneous operation. Also, since the WRITE voltage of the capacitor for data storage decreases to a low level, the data-hold time decreases, resulting in accidental data erasure and/or an increased soft error rate. Therefore, while capacitor 23 is being charged, even if the other circuit elements are able to operate, the next operation of the circuit elements should not be started. Thus, one-operation cycle time is prolonged by the period (20 to 30 nsec) necessary for precharging capacitor 23. (First defect)
Recently, dynamic RAMs have been developed, which have an internal address counter, to enable an auto-refresh operation to be performed without the need for externally supplying an address signal. In such a RAM, a normal (or regular) data write/read operation (to be referred to hereinafter as a normal operation) and a refresh operation can be performed separately. In order to shorten the refresh time, it is proposed to divide the memory cell array into a number of groups (each consisting of several columns), and to drive more word lines (of each divided group) in a parallel manner, than in the normal operation. In this case, however, if a voltage bootstrap used in a conventional memory device is adapted, since the increased voltage actually applied to a word line is determined in accordance with a ratio of the capacitance of capacitor 23 to the parasitic capacitance on a path from output node N3 to the word line (FIG. 2), the following disadvantages arise. That is, when more word lines than in a normal operation are to be driven in a parallel manner, in a refresh operation, and if the capacitance of capacitor 23 is to be small, in consideration of the normal operation, the potential of the word line becomes insufficient during the refresh operation, resulting in accidental data erasure or an increased soft error rate.
On the other hand, if capacitor 23 has a large capacitance, in consideration of the refresh operation, the potential of the word line becomes unnecessarily high during the normal operation, thereby materially degrading the reliability of the gate oxide film of a selection MOS transistor in the memory cell, or of a MOS transistor in the row decoder. In other words, if the word line potential is unnecessarily high, the gate leakage of the MOS transistor is increased or the gate threshold level thereof is shifted to a high value, thereby degrading the transistor element. In a worst case situation, the gate is damaged. In this manner, in a conventional memory device, different numbers of word or bit lines cannot be driven in a parallel manner, in normal and refresh operations. (Second defect)